Power amplifier design using FETs is a well-developed field of electronic circuit design, with the FET defined as a device having a gate electrode and source and drain electrodes. The gate electrode is supplied with a gate bias voltage which in turn sets the bias current (Ids). The bias circuit is completed with the source and drain electrodes, with a source-drain voltage (Vds) applied between them. The optimum operational bias current (Ids) and operational bias voltage (Vds) varies from mode to mode of amplifier operation.
Where FETs are applied in power amplifiers in the telecommunications industry, including portable cellular telephones, a power saving feature is often desirable. This is typically achieved by significant attenuation of the input power level to the amplifier, combined with pinching off the bias current. This shifts the FET operation into a standby mode in response to a transmit/receive command. Additional FET operational states involving adjustment of the input power as well as the source-drain current include a high power state, a reduced power state and a linear, low power state.
Typical design problems associated with operation of an FET in a power amplifier include proper choice of the operating point so that the circuit operates in the linear portion of the FET transfer characteristics in which there is gain. This in known as a biasing problem, in which the gate electrode voltage must be established to allow for dynamic operation within the linear amplification range. This choice is complicated by the need to design the circuit so that the FET does not exceed its maximum power dissipation range, and improper bias design may allow the operating point to shift with temperature in such a way as to burn out the transistor.
The bias problem is further complicated by an unwanted effect known as thermal runaway, which is due to the thermal resistance between the junctions of the transistor and the transistor case. During operation, the power dissipated heats the junction and causes a change in the transistor characteristics, and with unfavorable bias conditions, this in turn causes an increase in the bias current, leading to further overheating. The heat dissipation is also a function of the ambient temperature, and worst case design requires anticipation of these factors.
In telecommunication applications, in addition to the usual problems associated with biasing the FET, the design is further complicated in systems providing time division duplex (TDD) communications and having features such as RF power output control and power saving modes. A complete summary of the design issues is presented as follows:
1) Power On control--high frequency power FET's inevitably require a positive/negative (dual) power source. When the power supply is applied to or disconnected from the unit, the biasing circuit must guarantee that the negative supply is applied to the FET gate electrode before the positive supply appears at the drain electrode. Otherwise, the FET may draw the maximum Ids and self-destruct from oscillations and inability to dissipate the resultant heat buildup. PA1 2) Prevent Thermal Runaway--FET biasing circuits which use the "open loop" method (no current sensing feedback) of adjusting Ids, via application of a voltage divider or adjustable voltage applied to the FET gate electrode, are vulnerable to thermal runaway. As mentioned above, this phenomenon occurs when the FET junction reaches a temperature where the gate voltage no longer regulates the channel conductance and the Ids avalanches to a self-destructing I.sub.DSS (saturated drain-source current). PA1 3) Insensitivity to temperature, power supply and device parameter variations--amplifier efficiency, gain and output power capability are all direct functions of Ids. As such, the less sensitive a biasing solution is to the aforementioned variations, the better. PA1 4) Versatility--the biasing scheme must accommodate a number of operational states via appropriate adjustment of the FET Ids: PA1 5) Enable/disable function--TDD operation and power save features require that the FET be transitioned quickly (within several .mu.s) from the Rx/Standby mode to one of the other three transmission modes. PA1 a voltage source means for providing a predetermined voltage in the source-drain voltage circuit portion; PA1 a plurality of fixed resistors being connectable to provide a selectable range of resistance values in the source-drain voltage circuit potion, PA1 controllable switching means for connecting said plurality of fixed resistors to select a particular resistance value corresponding to one of four predetermined amplifier operating modes, said selected resistance value establishing a source-drain current level associated with a selected one of said predetermined amplifier operating modes; and PA1 control means for controlling said switching means in response to the command, to select said amplifier operating mode.
a) saturated, high power state (high Ids) PA2 b) saturated, reduced power state (medium Ids) PA2 c) linear, low power state (minimal Ids) PA2 d) standby/Rx (receiving) state--no input/output (FET pinched off)
Existing solutions to the FET biasing problem include an open loop method, which involves adjusting the gate electrode voltage. Since direct measurement of the source-drain current is not easily achieved, the gate electrode voltage Vg is tuned while a more readily measurable parameter, such as output power, is observed. However, this approach is particularly vulnerable to the the thermal runaway problem due to lack of feedback.
Such an open loop method involves using a read-only memory to store gate bias voltage data for selection depending on the type of FET used, with a D/A converter to convert the digital value to an analog voltage for application to the gate electrode, as described in U.S. Pat. No. 5,278,517 to Fujita.
Another solution to the FET biasing problem is a closed loop approach, which provides feedback via a sensing resistor and error amplifier as a direct method of voltage tracking for setting the desired Ids and maintaining this setting over a wide temperature range. This approach, however, requires tracking of the error and when the power is first applied, the integrator delay allows for the possibility of a destructive surge in source-drain current. The integrator delay also prevents rapid transitions between operating modes, and a voltage reference adjustment is needed.
Examples of a direct control, closed loop approach to FET biasing so as to maintain the operating point are described in U.S. Pat. No. 5,442,322 to Kornfeld, U.S. Pat. No. 5,585,746 to Franke, and Japanese patent JP 09121126 A, to Oki Electric Ind. Co. Ltd.
As described above, in light of the many problems associated with biasing the FET in applications where there are different output power levels and rapid mode switching, it would be desirable to provide easily controllable FET biasing and insure safe operation despite temperature and loading fluctuations.